1. Technical Field
The present invention relates to a method for manufacturing a ferroelectric memory device and a ferroelectric memory device.
2. Related Art
Ferroelectric memory devices (FeRAM) are nonvolatile memory devices capable of low voltage and high-speed operation, and their memory cells can be each formed from one transistor and one capacitor (1T/1C). Accordingly, ferroelectric memory devices can achieve integration at the same level of that of DRAM, and are therefore expected as large-capacity nonvolatile memories.
To maximize the ferroelectric properties of the ferroelectric capacitors composing a ferroelectric memory device, the crystal orientation in each of the layers composing a ferroelectric capacitor is critical. In particular, to control the crystal orientation of the ferroelectric film, crystal orientation and flatness must be controlled from a lower electrode film disposed below the ferroelectric film. On the other hand, a stack structure, in which capacitors are formed on contact plugs connected to transistors, is known for improving the integration level of the capacitors, as described for example in Japanese Laid-open Patent Application JP-A-2004-134692.
In capacitors disposed in a stacked structure, a ferroelectric film is formed on two different surfaces, i.e., surfaces of a dielectric film and a contact plug, such that controlling the crystal orientations in these films is very important. Furthermore, step differences of recesses that are formed above the contact plugs cause a problem because they deteriorate the flatness and therefore damage the crystal orientation controllability. To address such a problem, the aforementioned document describes a technique which includes, after forming the contact plug, forming a conductive hydrogen barrier film over the whole surface of the contact plug, planarizing the whole surface by a CMP method until the recess is filled, and forming a lower electrode thereon.
However, if the conductive hydrogen barrier film composed of TiN or the like is merely planarized by a CMP method, like the aforementioned technique, a high resistance layer is formed at a surface layer portion of the conductive hydrogen barrier film when planarized due to the slurry used in this CMP method. In other words, when the slurry used in the CMP method is acidic, a thin oxide film is formed at a surface layer portion of the film after planarization, which forms a high resistance layer. Furthermore, even when the slurry is neutral, a very thin oxide film is formed at a surface layer portion of the film after planarization, which also forms a high resistance layer. Then, when the lower electrode of the capacitor is disposed on the high resistance layer thus formed, the resistance between the contact plug and the lower electrode elevates, which deteriorates the characteristics of the ferroelectric memory device.